[PATCH 02/24] RISC-V sim: Fix for jalr.

[Jim Wilson]

From: Palmer Dabbelt <palmer@dabbelt.com>

When rd and rs1 are the same reg, must read rs1 before writing rd.
Jal is also fixed for consistency.

	sim/riscv/
	* sim-main.c (execute_i): In case MATCH_JAL, move store_rd call
	after assignment to pc.  In case MATCH_JALR, likewise.
---
 sim/riscv/sim-main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index ccab3ba..ddc1060 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -417,14 +417,14 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_JAL:
       TRACE_INSN (cpu, "jal %s, %" PRIiTW ";", rd_name,
 		  EXTRACT_JTYPE_IMM (iw));
-      store_rd (cpu, rd, cpu->pc + 4);
       pc = cpu->pc + EXTRACT_JTYPE_IMM (iw);
+      store_rd (cpu, rd, cpu->pc + 4);
       TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
       break;
     case MATCH_JALR:
       TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm);
-      store_rd (cpu, rd, cpu->pc + 4);
       pc = cpu->regs[rs1] + i_imm;
+      store_rd (cpu, rd, cpu->pc + 4);
       TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
       break;
 
-- 
2.7.4